| NAME |
PTEST -- TESTs a logic address (PRIVILEGED) |
| SYNOPSIS |
| PTESTR | <FC>,<ea>,#<level> |
| PTESTR | <FC>,<ea>,#<level>,An |
| PTESTW | <FC>,<ea>,#<level> |
| PTESTW | <FC>,<ea>,#<level>,An |
No size specs.
|
| FUNCTION |
This instruction examines the ATC, if level is equal to zero,
a research in the translation tables is made, if level is different
of zero (1 to 7), then sets MMUSR bits.
This instruction can also store, in an address register An, physical
address encountred to last level of its research.
PTESTR or PTESTW version is used to simulate a read or write cycle and
like this, according to the informations founds, exactly set MMUSR.
MMUSR bits are set of the following manner:
| MMUSR bits | PTEST level 0 | PTEST level > 0 |
|---|
| B (bit 15) |
This bit is set if the bit "Error Bus (B)" of the ATC is set. |
This bit is set if a bus error is generated during research inthe tables. |
| L (bit 14) |
This bit is cleared |
This bit is set if an index overflow a limit during a research. |
| S (bit 13) |
This bit is cleared |
This bit is set for indicating a privilege violation: if S bit of one
of the descriptors met is set and the FC2 bit mentioned in the instruction
is cleared (user access). S isn't defined if the bit I of MMUSR is set. |
| W (bit 11) |
This bit is set if the bit WP in entry of the examined ATC is set. Undefined if I is set. |
This bit is set if WP bit of one of the descriptors encountred is set. Undefined if I is set. |
| I (bit 10) |
This bit is set if required logic address isn't in the ATC or if the bit B of this entry is set. |
This bit is set if one of the descriptors encountred isn't valid (DT = 0) or if B
or L of MMUSR are set during research. |
| M (bit 9) |
This bit is set if the bit M of designed entry is set. Undefined if I is set. |
This bit is set if the encountred page descriptor has its bit M set. Undefined if I is set. |
| T (bit 6) |
This bit is set if mentioned logic address is part of defined window by TT0 and/or TT1. |
This bit is cleared. |
| N (bits 2 to 0) |
This field is cleared |
This field represents the number of level accessed during table research. |
<FC> operand can be mentioned:
- in immediate.
- by the three lower bits of a data register.
- by the register SFC or DFC.
|
| FORMAT |
| | <ea> |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | MODE | REGISTER |
| 1 | 0 | 0 | LEVEL | R/W | A | REG | FC |
R/W field indicates type of access used for research:
| 0 | -> | write access. |
| 1 | -> | read access. |
FC field indicates value of Function Codes of the address to test
| 10XXX | The Function Codes are XXX. |
| 01DDD | The Function Codes are the bits 2 to 0 of a DDD data register. |
| 0000 | The Function Codes are specified in SFC. |
| 0001 | The Function Codes are specified in DFC. |
Bit A specifies address register option:
| 0 | -> | no address register |
| 1 | -> | address of last accessed descriptor is put in the register specified by REG. |
REG field indicates, if A = 1 the number of address register. Else
if A = 0, REG = 0.
LEVEL field indicates the highest logic level to go during research;
if test in the ATC, LEVEL = 0.
|
| REGISTER |
<ea> specifies logic address to test, allowed addressing modes are:
| Addressing Mode | Mode | Register |
|---|
| Dn | - | - |
| An | - | - |
| (An) | 010 | No reg. An |
| (An)+ | - | - |
| -(An) | - | - |
| (d16,An) | 101 | No reg. An |
| (d8,An,Xi) | 110 | No reg. An |
| (bd,An,Xi) | 110 | No reg. An |
| ([bd,An,Xi]od) | 110 | No reg. An |
| ([bd,An],Xi,od) | 110 | No reg. An |
|
| Abs.W | 111 | 000 |
| Abs.L | 111 | 001 |
| (d16,PC) | - | - |
| (d8,PC,Xi) | - | - |
| (bd,PC,Xi) | - | - |
| ([bd,PC,Xi],od) | - | - |
| ([bd,PC],Xi,od) | - | - |
| #data | - | - |
|
|
| RESULT |
Not affected. |
