NAME	PFLUSH -- Invalidate one or several entries in the ATC (PRIVILEGED)
SYNOPSIS	PFLUSHA PFLUSH <FC>,#<FC validation> PFLUSH <FC>,#<FC validation>,<ea> No size specs.
FUNCTION	Those three instructions are used to invalidate one or several entries of the ATC (PMMU cache), i.e. to set the validation bits following to those zero entries. PFLUSHA invalidate all the 22 entries of cache. PFLUSH <FC>,#<FC validation> invalidate entry which follows mentionned Function Codes. PFLUSH <FC>,#<FC validation>,<ea> invalidate entry which address is specified in the destination, of course in taking care of Function Codes. FC validation bits allow to take care of 3 FC bits else only some of these bits. The status register of the PMMU, MMUSR, isn't affected by this instruction. <FC> operand can be mentioned: in immediate. by the three lower bits of a data register. by the register SFC or DFC.
FORMAT	<ea> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 0 0 0 0 0 MODE REGISTER 0 0 1 MODE 0 0 FC FC             VALIDATION   MODE field indicates the type of PFLUSH: 001 -> invalidation of all entries. 100 -> invalidation by Function Codes. 110 -> invalidation by the Function Codes and <ea>. FC VALIDATION field indicates the FC bits to take care of. FC field indicates value of Function Codes of the entry to invalidate. 10XXX The Function Codes are XXX. 01DDD The Function Codes are the bits 2 to 0 of a DDD data register. 0000 The Function Codes are specified in SFC. 0001 The Function Codes are specified in DFC.
REGISTER	<ea> specifies address to invalidate, allowed addressing modes are: Addressing Mode Mode Register Dn - - An - - (An) 010 No reg. An (An)+ - - -(An) - - (d16,An) 101 No reg. An (d8,An,Xi) 110 No reg. An (bd,An,Xi) 110 No reg. An ([bd,An,Xi]od) 110 No reg. An ([bd,An],Xi,od) 110 No reg. An Addressing Mode Mode Register Abs.W 111 000 Abs.L 111 001 (d16,PC) - - (d8,PC,Xi) - - (bd,PC,Xi) - - ([bd,PC,Xi],od) - - ([bd,PC],Xi,od) - - #data - -
RESULT	Not affected.

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