NAME	DIVS, DIVSL -- Signed divide
SYNOPSIS	<ea>,Dn 32/16 -> 16r:16q DIVS.L <ea>,Dq 32/32 -> 32q (68020+) DIVS.L <ea>,Dr:Dq 64/32 -> 32r:32q (68020+) DIVSL.L <ea>,Dr:Dq 32/32 -> 32r:32q (68020+) Size = (Word, Long)
FUNCTION	Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The instruction has a word form and three long forms. For the word form, the destination operand is a long word and the source operand is a word. The resultant quotient is placed in the lower word of the destination and the resultant remainder is placed in the upper word of the destination. The sign of the remainder is the same as the sign of the dividend. In the first long form, the destination and the source are both long words. The quotient is placed in the longword of the destination and the remainder is discarded. The second long form has the destination as a quadword (eight bytes), specified by any two data registers, and the source is a long word. The resultant remainder and quotient are both long words and are placed in the destination registers. The final long form has both the source and the destination as long words and the resultant quotient and remainder as long words.
FORMAT	In the case of DIVS.W:   <ea> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 REGISTER 1 1 1 MODE REGISTER "REGISTER" indicates the number of data register. In the case of DIVS.L and of DIVL.L:   <ea> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 0 1 1 0 0 0 1 MODE REGISTER 0 Dq REGISTER 1 SIZE 0 0 0 0 0 0 0 Dr REGISTER "Dq REGISTER" indicates the number of data register for destination operand. This register first contains 32 bits of low weight of dividend, and after the value of quotient on 32 bits. "SIZE" specifies if dividend is on 32 or 64 bits: 0-> 32 bits dividend placed in Dq. 1-> 64 bits dividend placed in Dr:Dq. "Dr REGISTER" indicates the number of data register for destination operand. This register first contains 32 bits of upper weight of dividend if "SIZE" = 1, and after the value of rest on 32 bits. If Dr and Dq represents the same register, only quotient on 32 bits is put in Dq. <ea> field specifies source operand, allowed addressing modes are: Addressing Mode Mode Register Dn 000 No reg. Dn An - - (An) 010 No reg. An (An)+ 011 No reg. An -(An) 100 NO reg. An (d16,An) 101 No reg. An (d8,An,Xi) 110 No reg. An (bd,An,Xi) 110 No reg. An ([bd,An,Xi]od) 110 No reg. An ([bd,An],Xi,od) 110 No reg. An Addressing Mode Mode Register Abs.W 111 000 Abs.L 111 001 (d16,PC) 111 010 (d8,PC,Xi) 111 011 (bd,PC,Xi) 111 011 ([bd,PC,Xi],od) 111 011 ([bd,PC],Xi,od) 111 011 #data 111 100
RESULT	X - Not affected N - Set if the quotient is negative, cleared otherwise. Undefined if overflow or divide by zero occurs. Z - Set if the quotient is zero, cleared otherwise. Undefined if overflow or divide by zero occurs. V - Set if overflow occurs, cleared otherwise. Undefined if divide by zero occurs. C - Always cleared. Notes: If divide by zero occurs, an exception occurs. If overflow occurs, neither operand is affected.

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